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ADV7612
Pin
Data Sheet
No.
66
67
68
69
70
71
72
73
Mnemonic
P3
P2
P1
P0
DVDDIO
DE
HS
VS/FIELD/ALSB
Type
Digital video output
Digital video output
Digital video output
Digital video output
Power
Miscellaneous digital
Digital video output
Digital video output
Description
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Video Pixel Output Port.
Digital I/O Supply Voltage (3.3 V).
DE (data enable) is a signal that indicates active pixel data.
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal. FIELD is a field synchronization output
signal in all interlaced video modes. VS or FIELD can be configured for this pin. ALSB
allows selection of the I 2 C address.
74
75
76
77
AP0
AP1
AP2
AP3
Miscellaneous digital
Miscellaneous digital
Miscellaneous digital
Miscellaneous ditial
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S.
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S.
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S.
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S.
78
79
80
AP4
SCLK/INT2
AP5
Miscellaneous ditial
Miscellaneous digital
Miscellaneous
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S.
A dual function pin that can be configured to output an audio serial clock or an Interrupt 2
signal.
Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio
output, HBR, DSD, DST, or I 2 S. Additionally, Pin AP5 can be configured to provide LRCLK.
81
82
83
84
85
86
MCLK/INT2
DVDD
SCL
SDA
INT1
RESET
Miscellaneous
Power
Miscellaneous digital
Miscellaneous digital
Miscellaneous digital
Miscellaneous digital
A dual function pin that can be configured to output an audio master clock or an Interrupt 2
signal.
Digital Core Supply Voltage (1.8 V).
I 2 C Port Serial Clock Input. SCL is the clock line for the control port.
I 2 C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user configuration.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7612 circuitry.
87
88
89
90
CS
PVDD
XTALP
XTALN
Miscellaneous digital
Power
Miscellaneous analog
Miscellaneous analog
Chip Select. This pin has an internal pull-down. Pulling this line up causes I 2 C state
machine to ignore I 2 C transmission.
PLL Supply Voltage (1.8 V).
Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator
Source to Clock the ADV7612 .
Crystal Input. Input pin for 28.63636 MHz crystal. This pin should be left unconnected if
XTALP is driven with 1.8 V clock signal.
91
92
93
94
95
96
97
98
99
100
DVDD
CEC
DDCB_SCL
DDCB_SDA
RXB_5V
HPA_B
DDCA_SCL
DDCA_SDA
RXA_5V
HPA_A/INT2
Power
Digital input/output
HDMI input
HDMI input
HDMI input
Miscellaneous digital
HDMI input
HDMI input
HDMI input
Miscellaneous digital
Digital Core Supply Voltage (1.8 V).
Consumer Electronic Control Channel.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.
5 V Detect Pin for Port B in the HDMI Interface.
Hot Plug assert signal output for HDMI Port B. This pin is 5 V tolerant.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
5 V Detect Pin for Port A in the HDMI Interface.
A dual function pin that can be configured to output Hot Plug assert signal (for HDMI
Port A) or an Interrupt 2 signal. This pin is 5 V tolerant.
Rev. E | Page 10 of 20
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